1. Technical Field
Example embodiments relate to a semiconductor memory device, and more particularly to a layout of a sub-word line driver circuit and a semiconductor memory device having a sub-word line driver circuit.
2. Description of the Related Art
Semiconductor memory devices are configured to store data into and read data from memory cells connected to word lines and bit lines. Memory cells connected to one word line are selected simultaneously based on a word line voltage that is applied to the one word line.
As storage capacity of a semiconductor memory device increases, more memory cells are connected to one word line and thus a current-driving capacity of a word line driver needs to be increased. When the current-driving capacity of the word line driver is limited, a delay in driving a selected word line connected to a relatively large number of memory cells becomes serious. To solve problems due to such delay, a word line may be divided into a plurality of sub-word lines, and the plurality of the sub-word lines may be driven by sub-word line drivers (SWD), respectively.
A sub-word line driver provides a sub-word line with a boost voltage having a higher level than a power supply voltage to select a relatively small number of memory cells connected to one sub-word line. The boost voltage is applied to a pull-up transistor such as a p-type metal oxide semiconductor (PMOS) included in the sub-word line driver. When the pull-up transistor operates repeatedly based on the boost voltage having a high voltage level, degradation such as a hot electron induced punch through (HEIP) may be caused and a standby current may be increased, thereby degrading a reliability of the sub-word line driver.